1. Field of the Invention
The present invention generally relates to semiconductor integrated circuit devices, and more particularly to a semiconductor integrated circuit device such as a one-chip microcomputer device. More specifically, the present invention relates to a data register provided in a data processing device such as a one-chip microcomputer.
2. Description of the Prior Art
FIG. 1 shows a one-chip microcomputer device. As shown in FIG. 1, the device includes a chip body 1, a CPU (Central Processing Unit) 2, a ROM (Read Only Memory) 3, a RAM (Random Access Memory) 4, a peripheral circuit 5, and an I/O (Input/Output) port 6. The ROM 3 is mainly used to store programs executed by the CPU 2. The RAM 4 is mainly used to temporarily store data. The peripheral circuit 5 is, for example, an A/D (Analog-to-Digital) converter, or a D/A (Digital-to-Analog) converter.
The CPU 2 is configured as shown in FIG. 2 which shows an essential part of the CPU 2. A program counter (PC) 7 outputs the address of an instruction to be fetched. An instruction register (IR) 8 stores the taken-out instruction. An instruction decoder (DEC) 9 decodes the instruction stored in the instruction register 8. A data register (DR) 10 is used as a "note or working area". An arithmetic and logic unit (ALU) 11 performs arithmetic and logical operations. Read data is output to read buses 12 and 13. A write bus 14 is used to supply the data register 10 with write data to be written into the data register 10.
FIG. 3 shows an essential part of the data register 10. As shown in FIG. 3, the data register 10 includes memory cells 15.sub.11 through 15.sub.45, write-use word WL.sub.12, WL.sub.22, WL.sub.32, WL.sub.42, WL.sub.13, WL.sub.23, WL.sub.33, and WL.sub.43. lines WL.sub.11, WL.sub.21, WL.sub.31, WL.sub.41, and read-use word lines Further, the data register 10 includes write-use bit lines BL.sub.11, BL.sub.12, BL.sub.21, BL.sub.22, BL.sub.31, BL.sub.32, BL.sub.41, BL.sub.42, BL.sub.51 and BL.sub.52, read-use bit lines BL.sub.13, BL.sub.14, BL.sub.23, BL.sub.24, BL.sub.33, BL.sub.34, BL.sub.43, BL.sub.44, BL.sub.53 and BL.sub.54.
The memory cells 15.sub.11 through 15.sub.45 have an identical circuit configuration. By way of example, the memory cell 15.sub.11 is shown in FIG. 4. The memory cell 15.sub.11 has an SRAM (Static Random Access Memory) cell structure, and includes a flip-flop 16 having two inverters 17 and 18 connected in a ring formation, two nMOS (n-channel Metal Oxide Semiconductor) transistors 19 and 20 for use in writing data, and two nMOS transistors 21 and 22 for use in reading data. These transistors 19-22 function as transfer gates.
When data is written into the memory cell 15.sub.11, the word line WL.sub.11 is switched to a high (H) level and the word lines WL.sub.12 and WL.sub.13 are switched to a low (L) level. The nMOS transistors 19 and 20 are turned ON, and the nMOS transistors 21 and 22 are turned OFF. Further, one of the bit lines BL.sub.11 and BL.sub.12 is switched to the high level and the other bit line is switched to the low level on the basis of the binary value indicated by data to be written into the memory cell 15.sub.11.
When data is read from the memory cell 15.sub.11 via the bit line BL.sub.13, the bit line BL.sub.13 is reset to the high level via a load. Further, the word line WL.sub.11 and WL.sub.13 are switched to the low level, and the word line WL.sub.12 is switched to the high level. Thus, the nMOS transistors 19, 20 and 22 are turned OFF, and the nMOS transistor 21 is turned ON. Hence, the potential of the bit line BL.sub.13 is detected.
When data is read from the memory cell 15.sub.11 via the bit line BL.sub.14, the bit line BL.sub.14 is reset to the high level via a load. Further, the word lines WL.sub.11 and WL.sub.12 are switched to the low level and the word line WL.sub.13 is switched to the high level. Thus, the nMOS transistors 19, 20 and 21 are turned OFF, and the nMOS transistor 22 is turned ON. Hence, the potential of the bit line BL.sub.14 is detected.
Turning to FIG. 3 again, the data register 10 includes an address decoder 23 for selecting the write-use word lines WL.sub.11, WL.sub.21, WL.sub.31, WL.sub.41, an address decoder 24 for selecting the read-use word lines WL.sub.12, WL.sub.22, WL.sub.32, WL.sub.42, an address decoder 25 for selecting the read use word lines WL.sub.13, WL.sub.23, WL.sub.33, and WL.sub.43. Further, the data register 10 includes a write selector 26 for selecting the write-use bit lines BL.sub.11, BL.sub.12, BL.sub.21, BL.sub.22, BL.sub.31, BL.sub.32, BL.sub.41, BL.sub.42, BL.sub.51 and BL.sub.52 in order to write data, and a decoder 27, which decodes a control signal supplied from the instruction decoder 9 and hence controls the selecting operation of the write selector 26. Further, the data register 10 includes read selector 28 and 30 for selecting the read-use bit lines BL.sub.13, BL.sub.14, BL.sub.23, BL.sub.24, BL.sub.33, BL.sub.34, BL.sub.43, BL.sub.44, BL.sub.53 and BL.sub.54 in order to read data, and decoder 29 and 31, which decode the control signals supplied from the instruction decoder 9 and hence controls the selecting operation of the read selector 28 and 30.
The writing via the write selector 26 and reading via the read selectors 28 and 30 can be simultaneously carried out under the condition that two word lines or more are not concurrently selected for the same row (the same address viewed from the address decoders 23-25). For example, the write operation on the memory cells 15.sub.11 -15.sub.15 specified by address 0 via the write selector 26, the first read operation on the memory cells 15.sub.21 -15.sub.25 specified by address 1 via the read selector 28, and the second read operation on the memory cells 15.sub.31 -15.sub.35 specified by address 2 via the read selector 30 can be simultaneously performed. The above-mentioned one-write two-read operation is needed to process instructions in a pipeline formation.
The memory cell shown in FIG. 4 uses four nMOS transistors 19-22, and hence the data register 10 having a large number of memory cells occupies a large area on the chip and needs a large chip area.